1. Field of the Invention
The present invention relates to a sticky bit value predicting circuit for use in a multiplication circuit.
2. Description of the Related Art
FIG. 9 shows a prior art mantissa multiplication circuit.
A product of a multiplicand X and a multiplier Y is calculated in a multiplier 10, the circuit is provided with, for example, a Wallace tree and a Booth recorder for a high speed processing. The multiplicand X and the multiplier Y each have xe2x80x981xe2x80x99 as a value of the most significant bit (MSB) and are normalized so as to respectively be 1xe2x89xa6X less than 2 and 1xe2x89xa6Y less than 2. The product Z is rounded in a rounding circuit 11 and a product ZHxe2x80x2 is obtained.
FIG. 10 is an illustration a sticky bit used in a rounding operation in a case where a multiplicand and a multiplier each are 8 bits and the product is 16 bits.
Since 1xe2x89xa6Z less than 4, the integral part of the product Z having bits Z15 to Z0 is comprised of higher-order two bits Z15 and Z14, wherein Z15=xe2x80x981xe2x80x99 or Z14=xe2x80x981.xe2x80x99
Denoting higher-order 8 bits of the product Z as ZH normalized as MSB=xe2x80x981xe2x80x99 before rounding, in a case where Z15 =xe2x80x980xe2x80x99 and Z14=xe2x80x981xe2x80x99, ZH is expressed as Z14 to Z7, and therefor the least significant bit (LSB) is Z7 and a round bit R is Z6. The sticky bit S is xe2x80x9c1xe2x80x9d when any one of Z5 to Z0 bits is xe2x80x981,xe2x80x99 or else the sticky bit S is xe2x80x9c0.xe2x80x9d A rounding operation on the product ZH is performed using the round bit R and the sticky bit S according to the IEEE (The Institute of Electrical and Electronic Engineers, Inc.) Binary Floating-Point Standard 754, and the result is Zxe2x80x2=ZH or Zxe2x80x2=ZH+1.
In a case where Z15=xe2x80x981,xe2x80x99 the product Z is right-shifted by one bit to normalize. Using Z15 to Z0 before this shifting, the LSB of the product ZH is Z8 and the round bit is Z7. The OR of Z7 and the provisional sticky bit S obtained before the shift is performed to obtain an actual sticky bit S.
If the sticky bit S is obtained with OR gates 12 to 16 after the product Z is obtained, it takes a long time to obtain a rounded product ZHxe2x80x2.
Considering such circumstances, U.S. Pat. No. 4,928,259 has provided a sticky bit value predicting circuit 20 shown in FIG. 9, whereby the sticky bit S is obtained in parallel with a multiplication operation.
Referring back to FIG. 10, the number M of trailing Os is equal to the sum of the number C of trailing 0s of the multiplicand X and the number D of trailing 0s of the multiplier Y. For example as shown in FIG. 10, in a case where C=2 and D=3, then M=5. In a case where Mxe2x89xa76, then S=xe2x80x980,xe2x80x99 and in a case where M less than 6, then S=xe2x80x981.xe2x80x99
Referring back to FIG. 9, in the sticky bit value predicting circuit 20, the numbers C and D of trailing 0s of the multiplicand X and the multiplier Y are obtained in priority encoders (trailing zero encoders) 21 and 22, respectively, the sum M of the numbers C and D of the trailing 0s are calculated in an adder 23, and M is compared with a predetermined value CONST in a comparator 24, thereby obtaining the sticky bit S as a result.
However, circuit scales of the priority encoders 21 and 22 are comparatively large. As described in U.S. Pat. No. 4,928,259, a priority encoder of 5 bits comprises thirteen encoders 21 of 4 bits provided at a first stage, three encoders 21 of 4 bits and three multiplexers with 4 inputs provided at a second stage, and one encoder 21 of 4 bits and one multiplexer with 4 inputs provided at a third stage.
Accordingly, it is an object according to the present invention to provide a sticky bit value predicting circuit with a simpler configuration and a semiconductor device provided with the same.
In the present invention, there is provided a sticky bit value predicting circuit for predicting a sticky bit value of a product of a first mantissa and a second mantissa, comprising: a bit pattern generation circuit for generating a bit pattern of sticky bit values for any number of trailing 0s of the second mantissa on the basis of a trailing zero bit pattern of the first mantissa; a priority encoder for providing a selection control value, corresponding to a bit position of xe2x80x981xe2x80x99 whose priority is higher with lower order bit side, in response to the second mantissa; and a sticky bit selection circuit for selecting one bit from the generated bit pattern as a sticky bit value depending on the selection control value.
With the present invention, since a bit pattern generation circuit and a sticky bit selection circuit each with a simpler configuration are employed instead of a prior art configuration including priority encoders, an adder and a comparator, a configuration of the sticky bit value predicting circuit becomes simpler as a whole, which in turn makes the circuit scale smaller than a prior art one.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.